The present invention relates generally to microprocessors, and more particularly, to branch prediction for a microprocessor.
Reduced Instruction Set Computing (RISC) microprocessors are well known. RISC microprocessors are characterized by a smaller number of instructions, which are relatively simple to decode, and by having all arithmetic/logic operations be performed register-to-register. RISC instructions are generally of only one length (e.g., 32-bit instructions). RISC instruction execution is of the direct hardwired type, as opposed to microcoding. There is a fixed instruction cycle time, and the instructions are defined to be relatively simple so that each instruction generally executes in one relatively short cycle.
A RISC microprocessor typically includes an instruction for a conditional branch operation. I.e., if a certain condition is present, then branch to a given location. It is known that a relatively small number of branch operations cause most of the branch mispredictions. For example, it has been suggested that 80 percent of the branch mispredictions result from 20 percent of the branch instructions for a given processor. Other branch operations are relatively easy to predict. For example, if an array access is preceded by a check for a valid array access, the check for a valid array access is accomplished in a typical RISC microprocessor by executing multiple conditional branches. These branches are generally easy to predict.
Speed of execution is highly dependent on the sequentiality of the instruction stream executed by the microprocessor. Branches in the instruction stream disrupt the sequentiality of the instruction stream executed by the microprocessor and generate stalls while the prefetched instruction stream is flushed and a new instruction stream begun.
Accordingly, the present invention provides software branch prediction filtering for a microprocessor. For example, the present invention provides a cost-effective and high performance implementation of software branch prediction filtering executed on a microprocessor that performs branch operations. By providing the software branch prediction filtering, many easy-to-predict branches can be eliminated from a hardware-implemented branch prediction table thereby freeing up space in the branch prediction table that would otherwise be occupied by the easy-to-predict branches. In other words, easy-to-predict branches waste entries in a limited-size branch prediction table and, thus, are eliminated from the branch prediction table. This robust approach to software branch prediction filtering provides for improved branch prediction, which is desired in various environments, such as a Java(trademark) computing environment. For example, this method can be used for various instruction sets such as Sun Microsystems, Inc.""s UltraJava(trademark) instruction set.
In one embodiment, a method for software branch prediction filtering for a microprocessor includes determining whether a conditional branch operation is xe2x80x9ceasyxe2x80x9d-to-predict and predicting whether to execute the branch operation based on software branch prediction. However, xe2x80x9chardxe2x80x9d-to-predict branches are predicted using a hardware branch prediction (e.g., a limited size hardware branch prediction table).
Other aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.